Personal computer systems are well known in the art. Personal computer systems in general, and IBM Personal Computers in particular, have attained widespread use for providing computer power to many segments of today's modern society. Personal computers can typically be defined as a desktop, floor standing, or portable microcomputer that is comprised of a system unit having a single central processing unit (CPU) and associated volatile and non-volatile memory, including all RAM and BIOS ROM, a system monitor, a keyboard, one or more flexible diskette drives, a fixed disk storage drive (also known as a "hard drive"), a so-called "mouse" pointing device, and an optional printer. One of the distinguishing characteristics of these systems is the use of a motherboard or system planar to electrically connect these components together. These systems are designed primarily to give independent computing power to a single user and are inexpensively priced for purchase by individuals or small businesses. Examples of such personal computer systems are IBM's PERSONAL COMPUTER AT (IBM PC/AT), IBM's PERSONAL SYSTEM/1 (IBM PS/1), and IBM's PERSONAL SYSTEM/2 (IBM PS/2).
Personal computer systems are typically used to execute software to perform such diverse activities as word processing, manipulation of data via spread-sheets, collection and relation of data in databases, display of graphics, design of electrical or mechanical systems using system-design software, etc.
In such computer systems, the components communicate via electrical signals. These electrical signals are typically carried by electrical connections between the system components. Typical types of electrical connections include metal traces on a printed circuit board (PCB), vias between different levels of multilayer PCBs, plated through holes, plugs, and individual wires connected from pin to pin of system components. Typically groups of electrical signals and groups of electrical connections which carry the electrical signals are referred to as a "bus." Thus, a reference to a "bus" can indicate a reference to a group of electrical signals, a group of electrical connections which carry the electrical signals, or a reference to both a group of electrical signals which form a protocol and a group of electrical connections which carry the electrical signals. Buses are made up of "bus lines." A reference to an individual "bus line" may refer to an electrical connection of a bus or an electrical signal of a bus.
Typical computer systems have several distinct buses: a host processor bus, a memory bus, and one or more peripheral buses. The host processor bus is unique to each processor and dictated by the architecture of that processor. The memory bus is usually standardized to one of several memory buses to allow common, inexpensive memory units to be used. For example, many systems of widely different architectures are designed to use common single in-line memory modules (SIMMs). The peripheral bus(es) have evolved into a number of standards. The Industry Standard Architecture (ISA) bus, the "MICROCHANNEL" Architecture (MCA) bus, and the Peripheral Component Interconnect (PCI) bus, are examples of very well known peripheral buses.
The buses in a system typically must share resources across the various buses. For example, both the host processor bus and the peripheral bus typically must have access to the memory bus. To avoid conflicts between buses attempting to access the same bus, arbiters are designed to arbitrate between the two or more buses requesting access to the same bus.
The current trend in the computer industry is to design systems with more than one peripheral bus, e.g., a system with a PCI bus and an ISA bus. Such systems can become complicated because the arbiters must take into account both peripheral buses when arbitrating accesses to the memory bus.
A particularly complicated system is a system having a PCI bus and an MCA bus. Both the PCI bus and the MCA bus allow bus masters to assume control of that particular bus. Therefore, both of these buses have arbiters for arbitrating control of their respective buses. Thus, a system with a PCI bus and an MCA bus must have four arbiters: (1) the memory bus arbiter, (2) the PCI bus arbiter, (3) the MCA bus arbiter, and (4) a multibus arbiter for arbitrating between the PCI bus arbiter and the MCA bus arbiter. Thus, the PCI bus arbiter and the MCA bus arbiter must be interfaced with the memory arbiter to determine which of the many bus masters may access the memory bus at any one time.
This particular configuration is even more complicated because the PCI bus and the MCA bus use different criteria for determining how their respective bus masters are given control of their respective buses. The MCA bus masters are designed to stay on the bus as long as possible to optimize bus utilization. On the other hand, the PCI bus is a packet bus; PCI bus masters are designed to acquire the bus, perform a short high-speed transfer, and leave the bus.
Prior art multibus arbiters use timers to allocate the memory bus between the various buses. This is rigid and can lead to an unequitable allocation of memory bus bandwidth between the various peripheral buses.
Therefore, it is desirable to provide a multibus arbiter that allows a dynamic and more equitable allocation of memory bus bandwidth between the various buses.
It is specifically desirable to provide a multibus arbiter that allows a dynamic and more equitable allocation of memory bus bandwidth between the PCI bus and the MCA bus.